This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Generally, an integrated circuit (IC) having components of a computing system provided on a single chip typically refers to system on a chip (SoC). The SoC is fabricated to include digital, analog, mixed-signal, and/or radio-frequency (RF) capability on a single chip substrate. SoC applications are useful for mobile electronic devices due to their low power consumption and minimal area impact in embedded systems.
In some applications, an SOC may include embedded memory, such as, e.g., static random access memory (SRAM). Due to a denser layout, SRAM may have a higher defect density than other logic circuits, and to improve yield of SRAM, redundant SRAM cells may be provided. Conventionally, at the time of wafer testing, faulty SRAM cells are replaced with redundant cells, and their address location is stored in fuses.
Typically, SRAM cells are arranged in an array pattern, and redundant cells are provided as a column or row in the same array as memory cell instances. For SRAM in an SOC, column redundancy is sufficient; however, if accumulated density of SRAM is large, then row redundancy may be used. For instance, FIG. 1 shows a conventional redundancy scheme 100 for an SRAM array 110 of memory cells arranged in columns (Col 0, Col 1, . . . , Col M) and rows (Row 0, Row 1, . . . , Row N).
Further, the SRAM array 110 includes a Redundant Row of memory cells that are used to replace faulty or defective SRAM memory cells. Conventionally, as shown, the Redundant Row of memory cells is provided as part of the SRAM array 110. Further, the SRAM array 110 includes an internal comparator 112 that is used to determine whether faulty or defective SRAM memory cells have been replaced with redundant memory cells.
Conventionally, when a repaired row is accessed, an incoming row address from an SoC is compared with a faulty row address, and if there is no match, then regular row decoding occurs; otherwise, a redundant row is accessed via a repaired address from a fuse. Unfortunately, this additional comparison for repaired memory as compared to fault free memory typically causes an increase in setup time for addresses of repaired memory. Further, this increased setup time may slow down the overall performance and speed of SOC. As such, this increase in address setup time due to additional comparison operations is a typical problem for conventional row redundancy schemes.